The present disclosure relates to computer processor architecture, and more specifically, to condition code generation for a processor pipeline.
Computer processors include a number of different circuitry for performing different operations on data. The instruction set architecture (ISA) can define the set of operations carried out by a particular processor. Processors may use a pipelined design and may also include functions such as in-order or out-of-order execution. A front end issue pipeline can process and then issue instructions to different execution units accordingly. For example, the issue pipeline can format instructions into a form (e.g., micro-instructions) that can be recognized by other components of the processor. These micro-instructions may then be executed in different execution units of a processor. A particular group of execution units are referred to as floating-point units.